netlink[ 0.000000] Booting(2)

[ 0.000000] Memory: 514740K/524288K available (3585K kernel code, 111K rwdata, 924K rodata, 236K init, 293K bss, 9548K reserved, 0K cma-reserved, 393216K highmem)

[ 0.000000] Virtual kernel memory layout:

[ 0.000000] vector: 0xffff0000 - 0xffff1000 ( 4 kB)

[ 0.000000] fixmap: 0xffc00000 - 0xfff00000 (3072 kB)

[ 0.000000] vmalloc : 0xc8800000 - 0xff800000 ( 880 MB)

[ 0.000000] lowmem: 0xc0000000 - 0xc8000000 ( 128 MB)

[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)

[ 0.000000] modules : 0xbf000000 - 0xbfe00000 (14 MB)

[ 0.000000] .text : 0xc0008000 - 0xc0388a60 (3587 kB)

[ 0.000000] .init : 0xc0471000 - 0xc04ac000 ( 236 kB)

[ 0.000000] .data : 0xc04ac000 - 0xc04c7d00 ( 112 kB)

[ 0.000000] .bss : 0xc04c7d00 - 0xc05114c0 ( 294 kB)

[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1

[ 0.000000] Hierarchical RCU implementation.

[ 0.000000] NR_IRQS:16 nr_irqs:16 16

[ 0.000000] L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x0a530000

[ 0.000000] L2C-310 enabling early BRESP for Cortex-A9

[ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9

[ 0.000000] L2C-310 ID prefetch enabled, offset 1 lines

[ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled

[ 0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB

[ 0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x7e530001

[ 0.000010] sched_clock: 64 bits at 700MHz, resolution 1ns, wraps every 4398046511103ns

[ 0.000024] clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0xa17102bcf3, max_idle_ns: 440795224838 ns

本文来自电脑杂谈，转载请注明本文网址：
https://www.pc-fly.com/a/jisuanjixue/article-64675-2.html