56f8300_fx8300_f8300配1060

56F8323Evaluation Module User Manual 56F8300 16-bit Digital Signal Controllers MC56F8323EVMUM Rev. 2 07/2005 freescale.com Document Revision History Version History Description of ChangeRev 1.0 Initial Public ReleaseRev 2.0 Updated look and feel TABLE OF CONTENTS Preface Preface-vii Chapter 1 Introduction1.1 56F8323EVM Architecture. . 1-21.2 56F8323EVM Configuration Jumpers . . . 1-31.3 56F8323EVM Connections. . 1-5 Chapter 2 Technical Summary 2.1 56F8323. . 2-3 2.2 RS-232 Serial Communications . . . 2-4 2.3 Debug Support . 2-82.3.1 JTAG Connector . . 2-82.3.2 Parallel JTAG Intece Connector . . . 2-9 2.4 External Interrupts. . . 2-11 2.5 Reset . . . 2-11 2.6 Power Supply . 2-12 2.7 Daughter Card Connectors . 2-142.7.1 Peripheral Daughter Card Expansion Connector. . 2-142.7.2 Memory Daughter Card Expansion Connector . . . 2-17 2.8 Serial 10-bit 4-channel D/A Converter Optional . . . 2-19 2.9 Motor Control PWM Signals and LEDs . 2-202.10 CAN Intece . 2-212.11 Software Feature Jumpers. . 2-222.12 Peripheral Expansion Connectors . 2-23 2.12.1 PWM Port A Expansion Connector. . 2-23 2.12.2 Serial Peripheral Intece #0 Expansion Connector. . . . 2-24 2.12.3 Serial Peripheral Intece #1 Expansion Connector. . . . 2-24 2.12.4 Serial Communications Port #0 Expansion Connector . . 2-25 2.12.5 Serial Communications Port #1 Expansion Connector . . 2-25 2.12.6 Encoder #0 / Quad Timer Channel A Expansion Connector. . . 2-26 2.12.7 Timer Channel C Expansion Connector . . . 2-26 2.12.8 FlexCAN Expansion Connector . . . . 2-27 2.12.9 A/D Port A Expansion Connector . . . 2-27 Table of Contents, Rev. 2Freescale Semiconductor i Preliminary 2.12.10 GPIO Port A Expansion Connector. . 2-28 2.12.11 GPIO Port B Expansion Connector. . 2-29 2.12.12 GPIO Port C Expansion Connector. . 2-29 2.12.13 IRQA / RESET / CLOCK Expansion Connector . 2-302.13 Test Points. . . . 2-30 Appendix A 56F8323EVM Schematics Appendix B 56F8323EVM Bill of Material MC56F8323EVM User Manual, Rev. 2ii Freescale Semiconductor Preliminary LIST OF FIGURES1-1 Block Diagram of the 56F8323EVM . 1-21-2 56F8323EVM Jumper Reference . . . . 1-31-3 Connecting the 56F8323EVM Cables. 1-5 2-1 Schematic Diagram of the RS-232 Intece. 2-4 2-2 Schematic Diagram of the Clock Intece . . 2-6 2-3 Schematic Diagram of the Debug LED Intece . . 2-7 2-4 Block Diagram of the Parallel JTAG Intece . . . . 2-9 2-5 Schematic Diagram of the User Interrupt Intece. . . . . 2-11 2-6 Schematic Diagram of the RESET Intece. . . . . 2-11 2-7 Schematic Diagram of the Power Supply . . 2-13 2-8 Serial 10-bit, 4-Channel D/A Converter . . . 2-19 2-9 PWM Intece and LEDs . . . . 2-202-10 CAN Intece . . . 2-2 12-11 Software Feature Jumpers . . . . 2-222-12 Typical Analog Input RC Filter. . . . . 2-28 List of Figures, Rev. 2Freescale Semiconductor iii Preliminary MC56F8323EVM User Manual, Rev. 2iv Freescale Semiconductor Preliminary LIST OF TABLES1-1 56F8323EVM Default Jumper Options . . 1-4 2-1 Flow Control Header Options . . . . 2-4 2-2 SCI1 Jumper Options . 2-5 2-3 RS-232 Serial Connector Description . . . 2-5 2-4 LED Control. . . 2-6 2-5 JTAG Connector Description. . . . . 2-8 2-6 Parallel JTAG Intece Disable Jumper Selection . . . 2-8 2-7 Parallel JTAG Intece Connector Description . . . . 2-10 2-8 Parallel JTAG Intece Voltage Selection Jumper . . 2-10 2-9 Peripheral Daughter Card Connector Description . . . 2-14 2-10 Memory Daughter Card Connector Description . . . . 2-17 2-11 D/A Header Description. . . 2-19 2-12 CAN Signal Isolation Jumper Options. . 2-21 2-13 CAN Header Description . . 2-22 2-14 PWM Port A Connector Description . . . 2-23 2-15 SPI #0 Connector Description . . . 2-24 2-16 SPI #1 Connector Description . . . 2-24 2-17 SCI #0 Connector Description . . . 2-25 2-18 SCI #1 Connector Description . . . 2-25 2-19 Timer A Signal Connector Description . 2-26 2-20 Timer Channel C Connector Description. . . . . 2-26 2-21 CAN Connector Description . . . . 2-27 2-22 A/D Port A Connector Description . . . . 2-27 2-23 GPIO Port A Connector Description . . . 2-28 2-24 GPIO Port B Connector Description . . . 2-29 2-25 GPIO Port C Connector Description . . . 2-29 2-26 IRQA / RESET / CLOCK Connector Description. . . 2-30 List of Tables, Rev. 2Freescale Semiconductor v Preliminary MC56F8323EVM User Manual, Rev. 2vi Freescale Semiconductor Preliminary Preface This reference manual describes in detail the hardware on the 56F8323 Evaluation Module. Audience This document is intended for application developers who are creating software for devices using the Freescale 56F8323 part. Organization This manual is organized into two chapters and two appendixes. ? Chapter 1, Introduction - provides an overview of the EVM and its features. ? Chapter 2, Technical Summary - describes in detail the 56F8323EVM hardware. ? Appendix A, 56F8323EVM Schematics - contains the schematics of the 56F8323EVM. ? Appendix B, 56F8323EVM Bill of Material - provides a list of the materials used on the 56F8323EVM board. Suggested Reading More documentation on the 56F8323 and the 56F8323EVM kit may be found at URL: Preface, Rev. 2Freescale Semiconductor vii PreliminaryNotation ConventionsThis manual uses the following notational conventions: Term or Value Symbol Examples Exceptions Active High Signals No special symbol A0 Logic One attached to the signal CLKO name Active Low Signals Noted with an WE In schematic drawings, Logic Zero overbar in text and in OE Active Low Signals may most figures be noted by a back- slash: /WE Hexadecimal Values Begin with a “$” $0FF0 symbol $80 Decimal Values No special symbol 10 attached to the 34 number Binary Values Begin with the letter “b” b1010 attached to the number b0011 Numbers Considered positive 5 Voltage is often shown as unless specifically -10 positive: +3.3V noted as a negative value Blue Text Linkable on-line ...refer to Chapter 7, License Bold Reference sources, ...see: paths, emphasis MC56F8323EVM User Manual, Rev. 2viii Freescale Semiconductor PreliminaryDefinitions, Acronyms, and AbbreviationsDefinitions, acronyms and abbreviations for terms used in this document are defined below forreference.A/D Analog-to-Digital; a method of converting Analog signals to Digital valuesADC Analog-to-Digital Converter; a peripheral on the 56F8323 partCAN Controller Area Network; a serial communications peripheral and methodCiA CAN in Automation; an international CAN user’s group that coordinates standards for CAN communications protocolsCTS Clear To SendD/A Digital-to-Analog; a method of converting Digital values to an Analog form56F8323 A 16-bit controller with motor control peripheralsEOnCE Enhanced On-Chip Emulation; a debug bus and port created by Freescale to enable a designer to create a low-cost hardware intece for a professional-quality debug environmentEVM Evaluation Module; a hardware platform which allows a customer to evaluate the silicon and develop his applicationFlash Nonvolatile Random Access MemoryFlexCAN Flexible CAN Intece Module; a peripheral on the 56F8323 partGPIO General Purpose Input and Output port on Freescale’s family of controllers; does not share pin functionallity with any other peripheral on the chip and can only be set as an input, output, or level-sensitive interrupt inputIC Integrated CircuitJTAG Joint Test Action Group; a bus protocol/intece used for test and debugLED Light Emitting DiodeLQFP Low-profile Quad Flat PackageMPIO Multi-Purpose Input and Output port on Freescale’s family of controllers; shares package pins with other peripherals on the chip and can function as a GPIO Preface, Rev. 2Freescale Semiconductor ix PreliminaryOnCE On-Chip Emulation, a debug bus and port created by Freescale to allow a means for low-cost hardware which provides a professional-quality debug environmentPCB Printed Circuit BoardPLL Phase Locked LoopPWM Pulse Width ModulationQuad Dec Quadrature Decoder; a peripheral on the 56F8323 partRAM Random Access MemoryR/C Resistor/Capacitor NetworkSRAM Static Random Access MemoryRTS Request to SendSCI Serial Communications Intece; a peripherial on Freescale’s family of controllersSPI Serial Peripheral Intece; a peripheral on Freescale’s family of controllersUART Universal Asynchronous Receiver/TransmitterWS Wait StateReferencesThe following sources were referenced to produce this manual: [1] DSP56800E Reference Manual , DSP56800ERM; Freescale Semiconductor [2] 56F8300 Peripheral User Manual, MC56F8300UM; Freescale Semiconductor [3] 56F8323 Technical Data, MC56F8323; Freescale Semiconductor [4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment, Version 1.0, CAN in Automation [5] CAN Specification 2.0B, BOSCH or CAN in Automation MC56F8323EVM User Manual, Rev. 2x Freescale Semiconductor PreliminaryChapter 1 IntroductionThe 56F8323EVM is used to demonstrate the abilities of the 56F8323 and to provide a hardwaretool allowing the development of applications that use the 56F8323.The 56F8323EVM is an evaluation module board that includes an 56F8323 part, peripheralexpansion connectors, a CAN intece, an RS-232 intece, a JTAG-to-PC Printer port inteceand a pair of daughter card connectors. The peripheral expansion connectors and daughter cardexpansion connectors are for signal monitoring and allow expansion for user features. The 56F8323EVM is designed for the following purposes: ? Allowing new users to become familiar with the features of the 56800E architecture. The tools and examples provided with the 56F8323EVM facilitate evaluation of the feature set and the benefits of the family. ? Serving as a platform for real-time software development. The tool suite enables the user to develop and simulate routines, download the software to on-chip SRAM or Flash, run it, and debug it using a debugger via the JTAG/Enhanced OnCE EOnCE port. The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user-developed software at full speed until the break conditions are satisfied. The ability to examine and modify all user-accessible registers, memory and peripherals through the EOnCE port greatly facilitates the task of the developer. ? Serving as a platform for hardware development. The hardware platform enables the user to connect external hardware peripherals. The on-board peripherals can be disabled, providing the user with the ability to reassign any and all of the controller's peripherals. The EOnCE port's unobtrusive design means that all memory on the Processor is available to the user. Introduction, Rev. 2Freescale Semiconductor 1-1 Preliminary1.1 56F8323EVM ArchitectureThe 56F8323EVM facilitates the evaluation of various features present in the 56F8323 part. The56F8323EVM can be used to develop real-time software and hardware products based on the56F8323. The 56F8323EVM provides the features necessary for a user to write and debugsoftware, demonstrate the functionality of that software and intece with the user'sapplication-specific device s . The 56F8323EVM is flexible enough to allow a user to fullyexploit the 56F8323's features to optimize the performance of his product, as shown inFigure 1-1. 56F8323 Optional 8.00MHz XTAL/EXTAL SPI #0 4-Channel D/A Crystal 10-Bit D/A Header RS-232 DSub SCI #1 Intece 9-Pin Reset Logic RESET SCI #0 Timer C Peripheral Peripheral Timer A Expansion Daughter Card Connectors Connector PWMA ADCA QuadDec #0 FlexCAN JTAG JTAG / EOnCE CAN Bus Connector CAN Intece Header Debug LEDs CAN Bus Parallel DSub JTAG Daisy Chain 25-Pin PWM LEDs Intece +3.3V & GND Power Supply +3.3VA & AGND +3.3V, +3.3VA, +3.0VREF +5V & +3.0VA Figure 1-1. Block Diagram of the 56F8323EVM MC56F8323EVM User Manual, Rev. 21-2 Freescale Semiconductor Preliminary 56F8323EVM Configuration Jumpers 1.2 56F8323EVM Configuration JumpersFifteen jumper groups, JG1-JG15 , shown in Figure 1-2, are used to configure various featureson the 56F8323EVM board. Table 1-1 describes the default jumper group settings. JG10 JG2 4 3 1 JG12 JG1 JG15 3 2 1 1 3 J9 J10 J16 J8 J15 J7 J12 J17 J18 J11 J5 J13 JG7 J15 JG10 J21 J19 JG11 J1 PWMA0 J14 Y1 PWMA1 PWMA2 JG1 JG2 MC56F8323EVM PWMA3 PWMA4 JG12 N J2 / 1 3 PWMA5 S PC0 PC1 U1 PC2 PC3 P PC5 JG7 JG11 JTAG JG3 JG5 JG8 JG6 JG8 JG3 JG9 J3 JG4 JG13 JG14 U9 U10 J6 U3 J4 S2 S1 3 1 P2 P1 P3 LED3 IRQA RESET JG5 4 2 JG9 1 JG4 JG14 3 JG6 JG13 Figure 1-2. 56F8323EVM Jumper Reference Introduction, Rev. 2Freescale Semiconductor 1-3 Preliminary Table 1-1. 56F8323EVM Default Jumper Options Jumper Jumpers Comment Group Connections JG1 Connect on-board 8.0MHz crystal input to EXTAL signal 1–2 JG2 Connect on-board 8.0MHz crystal input to XTAL signal 1–2 JG3 Enable on-board Parallel JTAG Host/Target Intece NC JG4 Enable RS-232 output NC JG5 Pass RXD1 & TXD1 signals to RS-232 level converter 1–2 & 3–4 JG6 Pass Temperature Diode signal to ANA7 input 1–2 JG7 Set user Jumper #0 to a 1 value 1–2 JG8 Set user Jumper #1 to a 1 value 1–2 JG9 SPI #0 Daisy Chain Optional--not populated on board by default NC JG10 CAN bus termination selected 1–2 JG11 Connect Analog Ground to Digital Ground NC JG12 Enable on-chip regulator 1–2 JG13 Pass RTS to CTS 1–2 JG14 Select +3.3V operation of on-board Parallel JTAG Host/Target Intece 1–2 JG15 Pass CAN_TX & CAN_RX signals to CAN tranceiver 1–2 & 3–4 MC56F8323EVM User Manual, Rev. 21-4 Freescale Semiconductor Preliminary 56F8323EVM Connections1.3 56F8323EVM ConnectionsAn interconnection diagram is shown in Figure 1-3 for connecting the PC and the external+12.0V DC/AC power supply to the 56F8323EVM board. Parallel Extension Cable 56F8323EVM PC P1 Connect cable P3 to Parallel / Printer port External with 2.1mm, +12V receptacle Power connector Figure 1-3. Connecting the 56F8323EVM CablesPerform the following steps to connect the 56F8323EVM cables: 1. Connect the parallel extension cable to the Parallel port of the host computer. 2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the 56F8323EVM board. This connection allows the host computer to control the board. 3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC power source. 4. Connect the 2.1mm output power plug from the external power supply into P3, shown in Figure 1-3, on the 56F8323EVM board. 5. Apply power to the external power supply. The green Power-On LED, LED13, will illuminate when power is correctly applied. Introduction, Rev. 2Freescale Semiconductor 1-5 Preliminary MC56F8323EVM User Manual, Rev. 21-6 Freescale Semiconductor PreliminaryChapter 2 Technical SummaryThe 56F8323EVM is designed as a versatile Flash-based microcontroller development card fordeveloping real-time software and hardware products to support a new generation of applicationsin servo and motor control; digital and wireless messaging; digital answering machines; featurephones; modems; and digital cameras. The power of the 16-bit 56F8323, combined with theon-board RS-232 intece, CAN intece, Daughter Card Expansion intece and parallelJTAG intece, makes the 56F8323EVM ideal for developing and implementing many motorcontrolling algorithms, as well as for learning the architecture and instruction set of the 56F8323processor.The main features of the 56F8323EVM, with board and schematic reference designators, include: ? MC56F8323, a 16-bit +3.3V/+2.5V processor in a 64-pin LQFP package operating at 60MHz [U1] ? 8.00MHz crystal oscillator for processor frequency generation [Y1] ? Optional external oscillator frequency input connectors [JG1 and JG2] ? Joint Test Action Group JTAG port intece connector for an external debug Host Target Intece [J3] ? On-board Parallel JTAG Host Target Intece, with a connector for a PC printer port cable [P1], including a disable jumper [JG3] ? On-board Parallel JTAG Host Taget Intece voltage level selector [JG14] ? RS-232 intece for easy connection to a host processor [U3 and P2], with a disable jumper [JG4] ? RS-232 RTS and CTS signal connector [JG13] ? CAN intece for high speed, 1.0Mbps, FlexCAN communications [U8 and J12] ? CAN bypass and bus termination [J13 and JG10] ? CAN signal to CAN transceiver isolation connector [JG15] ? Peripheral Daughter Card Expansion Connector, which allows the user to attach his own SCI, SPI, PWM, Quad Decoder or GPIO-compatible peripherals to the Processor [J1] Technical Summary, Rev. 2Freescale Semiconductor 2-1 Preliminary ? Memory Daughter Card Expansion Connector, which allows the user to attach additonal power and grounds[J2] ? Connector which allows the user to attach his own SCI #0 / MPIO-compatible peripheral [J21] ? Connector which allows the user to attach his own SCI #1 / MPIO-compatible peripheral [J17] ? Connector which allows the user to attach his own SPI #0 / MPIO-compatible peripheral [J8] ? Connector which allows the user to attach his own SPI #1 / MPIO-compatible peripheral [J15] ? Connector which allows the user to attach his own PWMA-compatible peripheral [J5] ? Connector which allows the user to attach his own CAN physical layer peripheral [J10] ? Connector which allows the user to attach his own Timer A / Encoder #0-compatible peripheral [J7] ? Connector which allows the user to attach his own Timer C-compatible peripheral [J9] ? Connector which allows the user to attach his own A/D port A-compatible peripheral [J6] ? Connector which allows the user to attach his own peripheral to GPIO Port A [J16] ? Connector which allows the user to attach his own peripheral to GPIO Port B [J18] ? Connector which allows the user to attach his own peripheral to GPIO Port C [J19] ? On-board power regulation from an external +12V DC-supplied power input [P3] ? Light Emitting Diode LED power indicator [LED13] ? Six on-board LEDs allow real-time debugging of user programs [LED1-6] ? Six on-board Port A PWM monitoring LEDs [LED7-12] ? Internal OCR_DIS Core Regulator selector [JG12] ? Temperature Sense Diode-to-ANA7 selector [JG6] ? Manual RESET push-button [S1] ? Manual interrupt push-button for IRQA [S2] ? General purpose jumper on GPIO PB3 [JG7] ? General purpose jumper on GPIO PB0 [JG8] ? Optional 4-Channel 10-bit Serial D/A, SPI for real-time user data display [U5] MC56F8323EVM User Manual, Rev. 22-2 Freescale Semiconductor Preliminary 56F8323 2.1 56F8323The 56F8323EVM uses a Freescale MC56F8323 part, designated as U1 on the board and in theschematics. This part will operate at a maximum external bus speed of 60MHz. A full descriptionof the 56F8323, including functionality and user information, is provided in these documents: ? 56F8323 Technical Data Sheet, MC56F8323 : Electrical and timing specifications, pin descriptions, device specific peripheral information and package descriptions this document ? 56F8300 Peripheral User Manual, MC56F8300UM : Detailed description of peripherals of the 56F8300 family of devices ? DSP56800E Reference Manual , DSP56800ERM : Detailed description of the 56800E family architecture, 16-bit core processor, and the instruction setRefer to these documents for detailed information about chip functionality and operation. Theycan be found on this URL: Technical Summary, Rev. 2Freescale Semiconductor 2-3 Preliminary2.2 RS-232 Serial CommunicationsThe 56F8323EVM provides an RS-232 intece by the use of an RS-232 level converter, MaximMAX3245EEAI, designated as U3. Refer to the RS-232 schematic diagram in Figure 2-1. TheRS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232-compatiblesignal levels and connects to the host’s serial port via connector P2. Flow control is not provided,but could be implemented using uncommitted GPIO signals and connected to the RTS and CTSsignals on JG13; see Table 2-1. The SCI1 port signals can be isolated from the RS-232 levelconverter by removing the jumpers in JG5; reference Table 2-2. The pin-out of connector P2 isdetailed in Table 2-3. The RS-232 level converter/transceiver can be disabled by placing ajumper at JG4. RS-232 56F8323 Level Converter Intece P2 JG5 1 TXD1 1 2 T1in 6 3 4 RXD1 R1out T1out 2 7 JG13 3 RTS 1 T2in R1in 8 CTS 2 R2out R2in 4 9 T2out x 5 +3.3V FORCEOFF Jumper Removed: JG4 Enable RS-232 1 Jumper Pin 1-2: 2 Disable RS-232 Figure 2-1. Schematic Diagram of the RS-232 Intece Table 2-1. Flow Control Header Options JG13 Pin # Signal 1 RTS to Transceiver 2 CTS from Transceiver MC56F8323EVM User Manual, Rev. 22-4 Freescale Semiconductor Preliminary RS-232 Serial Communications Table 2-2. SCI1 Jumper Options JG5 Pin # Signal Pin # Signal 1 TXD1 2 TXD to RS-232 Transceiver 3 RXD1 4 RXD from RS-232 Transceiver Table 2-3. RS-232 Serial Connector Description P2 Pin # Signal Pin # Signal 1 Jumper to 6 & 4 6 Jumper to 1 & 4 2 TXD 7 CTS 3 RXD 8 RTS 4 Jumper to 1 & 6 9 NC 5 GNDThe 56F8323EVM uses on-chip 8.00MHz relaxation oscillator or the on-board 8.00MHz crystal,Y1, connected to its External Crystal Inputs, EXTAL and XTAL. To achieve its maximuminternal operating frequency, the 56F8323 uses its internal PLL to multiply this input clockfrequency. Additionally an external oscillator source can be connected to the device by using theoscillator bypass connectors, JG1 and JG2; see Figure 2-2. If the input frequency is above8MHz, then the EXTAL input should be jumpered to ground by adding a jumper between JG1pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If the input frequency isbelow 4MHz, then the input frequency can be injected on JG1’s pin 2. Technical Summary, Rev. 2Freescale Semiconductor 2-5 Preliminary EXTERNAL OSCILLATOR HEADERS 56F8323 JG1 1 2 EXTAL 3 8.00MHz JG2 1 2 XTAL Figure 2-2. Schematic Diagram of the Clock InteceSix on-board Light-Emitting Diodes, LEDs , are provided to allow real-time debugging for userprograms. These LEDs will allow the programmer to monitor program execution without havingto stop the program during debugging; refer to Figure 2-3. Table 2-4 describes the control ofeach LED. Table 2-4. LED Control Controlled by User LED Color Signal LED1 RED GPIO Port C Bit 0 LED2 YELLOW GPIO Port C Bit 1 LED3 GREEN GPIO Port C Bit 2 LED4 RED GPIO Port C Bit 3 LED5 YELLOW GPIO Port C Bit 4 LED6 GREEN GPIO Port C Bit 5 MC56F8323EVM User Manual, Rev. 22-6 Freescale Semiconductor Preliminary RS-232 Serial CommunicationsSetting PC0, PC1, PC2, PC3, P or PC5 to a Logic One value will turn on the associated LED. 56F8323 INVERTING BUFFER +3.3V RED LED PC0 YELLOW LED PC1 GREEN LED PC2 RED LED PC3 YELLOW LED P GREEN LED PC5 Figure 2-3. Schematic Diagram of the Debug LED Intece Technical Summary, Rev. 2Freescale Semiconductor 2-7 Preliminary2.3 Debug SupportThe 56F8323EVM provides an on-board Parallel JTAG Host Target Intece and a JTAGintece connector for external Target Intece support. Two intece connectors are providedto support each of these debugging approaches. These two connectors are designated the JTAGconnector and the Host Parallel Intece Connector.2.3.1 JTAG ConnectorThe JTAG connector on the 56F8323EVM allows the connection of an external Host TargetIntece for downloading programs and working with the 56F8323’s registers. This connector isused to communicate with an external Host Target Intece which passes information and databack and forth with a host processor running a debugger program. Table 2-5 shows the pin-outfor this connector. Table 2-5. JTAG Connector Description J3 Pin # Signal Pin # Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 +3.3V 12 NC 13 DE 14 TRSTWhen this connector is used with an external Host Target Intece, the parallel JTAG inteceshould be disabled by placing a jumper in jumper block JG3. Refer to Table 2-6 for this jumper’sselection options. Table 2-6. Parallel JTAG Intece Disable Jumper Selection JG3 Comment No jumpers Enable On-board Parallel JTAG Intece 1–2 Disable on-board Parallel JTAG Intece MC56F8323EVM User Manual, Rev. 22-8 Freescale Semiconductor Preliminary Debug Support2.3.2 Parallel JTAG Intece ConnectorThe Parallel JTAG Intece Connector, P1, allows the 56F8323 to communicate with a ParallelPrinter Port on a Windows PC; reference Figure 2-4. Using this connector, the user candownload programs and work with the 56F8323’s registers. Table 2-7 shows the pin-out for thisconnector. When using the parallel JTAG intece, the jumper at JG3 should be removed, asshown in Table 2-6. A jumper at JG14 selects the Parallel Printer Port’s intece voltagebetween +3.3V and +5.0V; see Table 2-8. DB-25 Connector Parallel JTAG Intece 56F8323 TDI IN OUT TDI TDO OUT IN TDO P_TRST IN OUT TRST TMS IN OUT TMS TCK IN OUT TCK P_RESET IN OUT RESET P_DE IN OUT DE +3.3V EN JG3 Jumper Removed: Enable JTAG I/F 1 2 Jumper Pin 1-2: Disable JTAG I/F Figure 2-4. Block Diagram of the Parallel JTAG Intece Technical Summary, Rev. 2Freescale Semiconductor 2-9 Preliminary Table 2-7. Parallel JTAG Intece Connector Description P1 Pin # Signal Pin # Signal 1 NC 14 NC 2 PORT_RESET 15 PORT_IDENT 3 PORT_TMS 16 N/C 4 PORT_TCK 17 N/C 5 PORT_TDI 18 GND 6 PORT_TRST 19 GND 7 PORT_DE 20 GND 8 PORT_IDENT 21 GND 9 PORT_VCC 22 GND 10 NC 23 GND 11 PORT_TDO 24 GND 12 NC 25 GND 13 PORT_CONNECT Table 2-8. Parallel JTAG Intece Voltage Selection Jumper JG14 Comment 1–2 +3.3V Parallel Printer Port Intece 2–3 +5.0V Parallel Printer Port Intece MC56F8323EVM User Manual, Rev. 22-10 Freescale Semiconductor Preliminary Reset2.4 External InterruptsOne on-board push-button switch is provided for external interrupt generation, as shown inFigure 2-5. S2 allows the user to generate a hardware interrupt for signal line IRQA. This switchallows the user to generate interrupts for user-specific programs. +3.3V 56F8323 10K S2 IRQA 0.1μF Figure 2-5. Schematic Diagram of the User Interrupt Intece2.5 ResetLogic is provided on the 56F8323 to generate an internal Power-On RESET. Additional resetlogic is provided to support the RESET signals from the JTAG connector, the Parallel JTAGIntece and the user RESET push-button, S1; refer to Figure 2-6. JTAG_RESET RESET RESET PUSHBUTTON MANUAL RESET S1 TRST JTAG_TAP_RESET Figure 2-6. Schematic Diagram of the RESET Intece Technical Summary, Rev. 2Freescale Semiconductor 2-11 Preliminary2.6 Power SupplyThe main power input to the 56F8323EVM, +12V DC at 1.2A, is through a 2.1mm coax powerjack. This input power is rectifie d to provide a DC supply input. This allows a user the option touse a +12V AC power supply. A 1.2Amp power supply is provided with the 56F8323EVM;however, less than 500mA is required by the EVM. The remaining current is available for customcontrol applications when connected to the Daughter Card connectors. The 56F8323EVMprovides +5.0V DC regulation for the CAN intece and additional regulators. The56F8323EVM provides +3.3V DC voltage regulation for the processor, memory, D/A, ADC,parallel JTAG intece and supporting logic; refer to Figure 2-7. Additional voltage regulationlogic provides a low noise +3.0V DC voltage reference to the controller’s A/D VREFH.Optionally, the processor’s A/D VREFH voltage can be provided by the +3.3VA supply on theboard by removing U15 and adding a 10 ohm resistor at R83. A jumper, JG11, and resistor, R68,are provided to allow the og and digital grounds to be isolated on the 56F8323EVM board.This allows the og ground reference point to be provided on a custom board attached to the56F8323EVM’s Daughter Card connectors. By removing R68, the AGND reference isdisconnected from the 56F8323EVM’s digital ground. By placing a jumper in JG11 or byreinstalling R68, the AGND is reconnected to the 56F8323EVM’s digital ground. Power appliedto the 56F8323EVM is indicated with a Power-On LED, referenced as LED13. Optionally, theuser can provide the +2.5 DC voltage needed by the controller’s core on connector J14 anddisable the on-chip CORE voltage regulator by removing the jumper on JG 12. Additonally, four0 ohm resistors or shorting wires must be added at R70, R71, R72 and R73, to allow the external+2.5V DC to pass to the 56F8323. MC56F8323EVM User Manual, Rev. 22-12 Freescale Semiconductor Preliminary Power Supply P3 +5.0V Power +5.0V DC +12V DC/AC Bridge Regulator Condition CAN Input Rectifier +3.3V +3.3V DC 56F8323 Regulator VDD_IO & PLL 56F8323EVM Parts J14 R70-R73 56F8323 +2.5V DC 1 VDD Core Ext In 2 Power On +3.3V +3.3VA DC 56F8323 Regulator ADCA R67 10? U15 +3.0V +3.0VA DC 56F8323 Regulator VREFH Figure 2-7. Schematic Diagram of the Power Supply Technical Summary, Rev. 2Freescale Semiconductor 2-13 Preliminary2.7 Daughter Card ConnectorsThe EVM board contains two daughter card expansion connectors. One connector, J1, containsthe processor’s peripheral port signals. The second connector, J2, contains addional power andground signals.2.7.1 Peripheral Daughter Card Expansion ConnectorThe processor’s peripheral port signals are connected to the Peripheral Daughter Card Expansionconnector, J1. The Peripheral Daughter Card connector is used to connect a user-specificdaughter card to the processor’s peripheral port signals. The Peripheral Port Daughter Cardconnector is a 100-pin high-density connector with signals for the IRQs, RESET, SPI, SCI,PWM, ADC and Quad Timer ports. Table 2-9 shows the Peripheral Daughter Card connector’ssignal-to-pin assignments. Table 2-9. Peripheral Daughter Card Connector Description J1 Pin # Signal Pin # Signal 1 +12V 2 +12V 3 GND 4 GND 5 +5.0V 6 +5.0V 7 GND 8 GND 9 +3.3V 10 +3.3V 11 GND 12 GND 13 NC 14 NC 15 NC 16 NC 17 GND 18 GND 19 PHASEA0 / PB7 / TA0 20 PHASEB0 / PB6 / TA1 21 INDEX0 / PB5 / TA2 22 HOME0 / PB4 / TA3 23 TC0 24 SS0 25 TC0 26 SS0 27 TC1 28 MISO0 MC56F8323EVM User Manual, Rev. 22-14 Freescale Semiconductor Preliminary Daughter Card Connectors Table 2-9. Peripheral Daughter Card Connector Description Continued J1 Pin # Signal Pin # Signal 29 IRQA 30 NC 31 TC1 32 TC3 33 PWMA0 34 PWMA1 35 PWMA2 36 PWMA3 37 PWMA4 38 PWMA5 39 GND 40 GND 41 ISA0 42 ISA1 43 ISA2 44 GND 45 FAULTA1 46 FAULTA0 47 NC 48 FAULTA2 49 GND 50 GND 51 NC 52 MISO0 53 NC 54 NC 55 NC 56 NC 57 GND 58 GND 59 NC 60 NC 61 NC 62 SS0 63 NC 64 NC 65 NC 66 NC 67 MOSI0 68 SS0 69 TC0 70 TC1 71 SCLK0 72 TC0 73 CAN_TX 74 CAN_RX 75 MOSI0 76 MISO0 77 SCLK0 78 SS0 Technical Summary, Rev. 2Freescale Semiconductor 2-15 Preliminary Table 2-9. Peripheral Daughter Card Connector Description Continued J1 Pin # Signal Pin # Signal 79 GND 80 GND 81 +VREFH 82 +VREFH 83 GNDA 84 GNDA 85 NC 86 NC 87 NC 88 NC 89 NC 90 NC 91 NC 92 NC 93 AN0 94 AN1 95 AN2 96 AN3 97 AN4 98 AN5 99 AN6 100 AN7 MC56F8323EVM User Manual, Rev. 22-16 Freescale Semiconductor Preliminary Daughter Card Connectors2.7.2 Memory Daughter Card Expansion ConnectorAdditional power and ground signals are connected to the Memory Daughter Card Expansionconnector, J2. Table 2-10 shows the port signal-to-pin assignments. Table 2-10. Memory Daughter Card Connector Description J2 Pin # Signal Pin # Signal 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 GND 10 GND 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 NC 18 NC 19 GND 20 GND 21 GND 22 GND 23 NC 24 NC 25 NC 26 NC 27 NC 28 NC 29 NC 30 NC 31 GND 32 GND 33 GND 34 GND 35 NC 36 NC 37 NC 38 NC 39 NC 40 NC 41 NC 42 NC Technical Summary, Rev. 2Freescale Semiconductor 2-17 Preliminary Table 2-10. Memory Daughter Card Connector Description Continued J2 Pin # Signal Pin # Signal 43 GND 44 GND 45 NC 46 NC 47 NC 48 NC 49 NC 50 NC 51 NC 52 GND 53 GND 54 GND 55 +3.3V 56 +3.3V 57 GND 58 GND 59 +5.0V 60 +5.0V MC56F8323EVM User Manual, Rev. 22-18 Freescale Semiconductor Preliminary Serial 10-bit 4-channel D/A Converter Optional 2.8 Serial 10-bit 4-channel D/A Converter Optional The 56F8323EVM board contains the provions for a user to provide a serial 10-bit, 4-channelD/A converter connected to the 56F8323’s SPI #0 port. The output pins are uncommitted and areconnected to a 4x2 header, J4, to allow easy user connections. Refer to Figure 2-8 for the D/Aconnections and Table 2-11 for the header’s pin-out. The D/A’s output full-scale range value canbe set to a value from +0.0V to +2.4V by a trimpot, R48. If this trimpot is preset to +2.05V, itwould provide approximately +2mV per step. If another device must be used with SPI #0’sMISO signal and with the D/A converter on the board, the daisy chain jumper, JG9, can be usedto extend or isolate the serial chain. 56F8323 MAX5251 D/A Connector MOSI0 DIN D/A 0 1 2 JG9 MISO0 2 1 DOUT D/A 1 3 4 D/A 2 5 6 SCLK0 SCLK D/A 3 7 8 SS0 CS VREF RSTO CL +3.3VA R48 Figure 2-8. Serial 10-bit, 4-Channel D/A Converter Table 2-11. D/A Header Description J4 Pin # Signal Pin # Signal 1 D/A Channel 0 2 AGND 3 D/A Channel 1 4 AGND 5 D/A Channel 2 6 AGND 7 D/A Channel 3 8 AGND Technical Summary, Rev. 2Freescale Semiconductor 2-19 Preliminary2.9 Motor Control PWM Signals and LEDsThe 56F8323 has one PWM unit. This unit contains six PWM output signals, three Fault inputsignals and three Phase Current sense inputs. The PWM signals are connected to a set of sixPWM LEDs via inverting buffers. The buffers are used to isolate and drive the processor’s PWMoutputs to the PWM LEDs. The PWM LEDs indicate the status of PWM signals; refer toFigure 2-9. Additionally, the PWM signals are routed out to a header, J5, and to the peripheraldaughter card connector, J1, for easy use by the end user. 56F8323 PWMA0 PWMA0 PWMA1 PWMA1 PWMA2 PWMA2 PWMA3 PWMA3 PWMA4 PWMA4 PWMA5 PWMA5 +3.3V Yellow LED LED7 Phase A Top Green LED LED8 Phase A Bottom LED Yellow LED LED9 Phase B Top Buffer Green LED LED10 Phase B Bottom Yellow LED LED11 Phase C Top Green LED LED12 Phase C Bottom Figure 2-9. PWM Intece and LEDs MC56F8323EVM User Manual, Rev. 22-20 Freescale Semiconductor Preliminary CAN Intece2.10 CAN InteceThe 56F8323EVM board contains a CAN physical-layer intece chip that is attached to theFlexCAN port’s CAN_RX and CAN_TX pins on the 56F8323. The EVM board uses a Philipshigh-speed, 1.0Mbps, physical layer intece chip, PCA82C250. Due to the +5.0V operatingvoltage of the CAN intece chip, a pull-up to +5.0V is required to level shift the Transmit Dataoutput line from the 56F8323. The CAN_TX and CAN_RX signals from the processor can beisolated by the connector at JG15; see Table 2-12. The CANH and CANL signals pass throughinductors before attaching to the CAN bus connectors. A primary, J12, and daisy chain, J13,CAN connectors are provided to allow easy daisy chaining of CAN devices. CAN bustermination of 120 ohms can be provided by adding a jumper to JG10. Refer to Table 2-13 forthe CAN connector signals and to Figure 2-10 for a connection diagram. +5.0V 56F8323 1K CAN Transceiver JG15 CAN_TX 1 2 TXD J12 CANH 4 CAN Bus 5 Connector CANL 3 CAN_RX 3 4 RXD J13 PCA82C250T 4 Daisy Chain CAN 5 Connector 3 JG10 1 CAN Bus 2 Terminator 120 Figure 2-10. CAN Intece Table 2-12. CAN Signal Isolation Jumper Options JG15 Pin # Signal Pin # Signal 1 CAN_TX 2 CAN_TX to CAN Transceiver 3 CAN_RX 4 CAN_RX from CAN Transceiver Technical Summary, Rev. 2Freescale Semiconductor 2-21 Preliminary Table 2-13. CAN Header Description J12 and J13 Pin # Signal Pin # Signal 1 NC 2 NC 3 CANL 4 CANH 5 GND 6 NC 7 NC 8 NC 9 NC 10 NC2.11 Software Feature JumpersThe 56F8323EVM board contains two software feature jumpers that allow the user to select“user-defined” software features. Two GPIO port pins, PB3 and PB0, are pulled high or low with10K ohm resistors on JG7 and JG8, respectively. Attaching a jumper between pins 1 and 2 willplace a high, or 1, on the port pin. Attaching a jumper between pins 2 and 3 will place a low, or 0,on the port pin; see Figure 2-11. 56F8323 JG7 +3.3V 10K 1 User Jumper SCLK0 / PB3 2 #0 3 10K JG8 +3.3V 10K 1 User Jumper SS0 / PB0 2 #1 3 10K Figure 2-11. Software Feature Jumpers MC56F8323EVM User Manual, Rev. 22-22 Freescale Semiconductor Preliminary Peripheral Expansion Connectors2.12 Peripheral Expansion ConnectorsThe EVM board contains a group of Peripheral Expansion Connectors used to gain access to theresources of the 56F8323. The following signal groups have expansion connectors: ? PWM Port A ? Serial Peripheral Intece Port #0 ? Serial Peripheral Intece Port #1 ? Serial Communications Port 0 ? Serial Communications Port 1 ? Encoder #0 / Timer Channel A ? Timer Channel C ? FlexCAN Port ? A/D Input Port A ? GPIO Port A ? GPIO Port B ? GPIO Port C ? IRQA / RESET / CLOCK2.12.1 PWM Port A Expansion ConnectorThe PWM port A is attached to this connector. Refer to Table 2-14 for connection information. Table 2-14. PWM Port A Connector Description J5 Pin # Signal Pin # Signal 1 PWMA0 / PA0 2 PWMA1 / PA1 3 PWMA2 / PA2 / SS1 4 PWMA3 / PA3 / MISO1 5 PWMA4 / PA4 / MOSI1 6 PWMA5 / PA5 / SCLK1 7 FAULTA0 / PA6 8 FAULTA1 / PA7 9 FAULTA2 / PA8 10 NC 11 ISA0 / PA9 12 ISA1 / PA10 13 ISA2/PA11 14 GND Technical Summary, Rev. 2Freescale Semiconductor 2-23 Preliminary2.12.2 Serial Peripheral Intece #0 Expansion ConnectorThe Serial Peripheral Intece #0 is an MPIO port attached to this connector. This port can beconfigured as a Serial Peripheral Intece or as a General Purpose I/O port. Refer to Table 2-15for connection information. Table 2-15. SPI #0 Connector Description J8 Pin # Signal Pin # Signal 1 MOSI0 / PB2 2 MISO0 / PB1 / RXD1 3 SCLK0 / PB3 4 SS0 / PB0 / TXD1 5 GND 6 +3.3V2.12.3 Serial Peripheral Intece #1 Expansion ConnectorThe Serial Peripheral Intece #1 is an MPIO port attached to this connector. This port can beconfigured as a Serial Peripheral Intece or as a General Purpose I/O port. Refer to Table 2-16for the connection information. Table 2-16. SPI #1 Connector Description J15 Pin # Signal Pin # Signal 1 MOSI1 / PWMA4 2 MISO1 / PWMA3 3 SCLK1 / PWMA5 4 SS1 / PWMA2 5 GND 6 +3.3V MC56F8323EVM User Manual, Rev. 22-24 Freescale Semiconductor Preliminary Peripheral Expansion Connectors2.12.4 Serial Communications Port #0 Expansion ConnectorThe Serial Communications Port #0 is an MPIO port attached to the SCI #0 expansion connector.This port can be configured as a Serial Communications Intece or as Timer Port C channels.Refer to Table 2-17 for connection information. Table 2-17. SCI #0 Connector Description J21 Pin # Signal Pin # Signal 1 TXD0 / TC0 2 RXD0 / TC1 3 GND 4 +3.3V 5 GND 6 +5.0V2.12.5 Serial Communications Port #1 Expansion ConnectorThe Serial Communications Port #1 is an MPIO port attached to the SCI #0 expansion connector.This port can be configured as a Serial Communications Intece or as SPI0 signals. Refer toTable 2-18 for connection information. Table 2-18. SCI #1 Connector Description J17 Pin # Signal Pin # Signal 1 TXD1 / SS0 2 RXD1 / MISO0 3 GND 4 +3.3V 5 GND 6 +5.0V Technical Summary, Rev. 2Freescale Semiconductor 2-25 Preliminary2.12.6 Encoder #0 / Quad Timer Channel A Expansion ConnectorThe Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansionconnector. This port can be configured as a Quadrature Decoder intece port, as a Quad Timerport, or as GPIO. Refer to Table 2-19 for the signals attached to the connector. Table 2-19. Timer A Signal Connector Description J7 Pin # Signal Pin # Signal 1 PHASEA0 / TA0 / PB7 2 PHASEB0 / TA1 / PB6 3 INDEX0 / TA2 / PB5 4 HOME0 / TA3 / PB4 5 GND 6 +3.3V2.12.7 Timer Channel C Expansion ConnectorThe Timer Channel C port is an MPIO port attached to the Timer C expansion connector. Thisport can be configured as a Quad Timer Intece, as SCI0 signals, or as GPIO. Refer toTable 2-20 for the signals attached to the connector. Table 2-20. Timer Channel C Connector Description J9 Pin # Signal Pin # Signal 1 TC0 / TXD0 / PC6 2 TC1 / RXD0 / TC5 3 GND 4 TC3 / P MC56F8323EVM User Manual, Rev. 22-26 Freescale Semiconductor Preliminary Peripheral Expansion Connectors2.12.8 FlexCAN Expansion ConnectorThe FlexCAN port is an MPIO port attached to the FlexCAN expansion connector. This port canbe configured as a FlexCAN Intece or as GPIO. Refer to Table 2-21 for connectioninformation. Table 2-21. CAN Connector Description J10 Pin # Signal Pin # Signal 1 CAN_TX / PC3 2 GND 3 CAN_RX / PC2 4 GND2.12.9 A/D Port A Expansion ConnectorThe 8-channel Analog-to-Digital conversion port A is attached to this connector. Refer toTable 2-22 for connection information. There is an RC network on each of the Analog Port Ainput signals; see Figure 2-12. Table 2-22. A/D Port A Connector Description J6 Pin # Signal Pin # Signal 1 AN0 2 AN1 3 AN2 4 AN3 5 AN4 6 AN5 7 AN6 8 AN7 9 GNDA 10 +VREFH Technical Summary, Rev. 2Freescale Semiconductor 2-27 Preliminary 100 ohm Analog Input To Controller Analog Port 0.0022μF Figure 2-12. Typical Analog Input RC Filter2.12.10 GPIO Port A Expansion ConnectorThe GPIO port A is attached to this connector. Refer to Table 2-23 for connection information. Table 2-23. GPIO Port A Connector Description J16 Pin # Signal Pin # Signal 1 PA0 / PWMA0 2 PA1 / PWMA1 3 PA2 / PWMA2 / SS1 4 PA3 / MISO1 / PWMA3 5 PA4 / PWMA4 / MOSI1 6 PA5 / SCLK1 / PWMA5 7 PA6 / FAULTA0 8 PA7 / FAULTA1 9 PA8 / FAULTA2 10 PA9 / ISA0 11 PA10 / ISA1 12 PA11 / ISA2 13 GND 14 +3.3V MC56F8323EVM User Manual, Rev. 22-28 Freescale Semiconductor Preliminary Peripheral Expansion Connectors2.12.11 GPIO Port B Expansion ConnectorThe GPIO port B is attached to this connector. Refer to Table 2-24 for connection information. Table 2-24. GPIO Port B Connector Description J18 Pin # Signal Pin # Signal 1 PB0 / SS0 2 PB1 / MISO0 3 PB2 / MOSI0 4 PB3 / SCLK0 5 PB4 / HOME0 6 PB5 / INDEX0 7 PB6 / PHASEB0 8 PB7 / PHASEA0 9 GND 10 +3.3V2.12.12 GPIO Port C Expansion ConnectorThe GPIO port C is attached to this connector. Refer to Table 2-25 for connection information. Table 2-25. GPIO Port C Connector Description J19 Pin # Signal Pin # Signal 1 PC0 / EXTAL 2 PC1 / XTAL 3 PC2 / CAN_RX 4 PC3 / CAN_TX 5 P / TC3 6 PC5 / TC1 7 PC6 / TC0 8 NC 9 GND 10 +3.3V Technical Summary, Rev. 2Freescale Semiconductor 2-29 Preliminary2.12.13 IRQA / RESET / CLOCK Expansion ConnectorThe IRQA / RESET / CLOCK signals are attached to this connector. Refer to Table 2-26 forconnection information. Table 2-26. IRQA / RESET / CLOCK Connector Description J11 Pin # Signal Pin # Signal 1 IRQA 2 RESET 3 EXTAL / PC0 4 XTAL / PC1 9 GND 10 +3.3V2.13 Test PointsThe 56F8323EVM board has a total of eleven test points: ? Analog Ground AGND [TP4] ? Four Digital Grounds GND [TP1, TP2, TP3 & TP10] ? Two +3.3V [TP6 & TP11] ? +3.3VA [TP5] ? Two +5.0V [TP7 & TP8] ? +12V [TP9] MC56F8323EVM User Manual, Rev. 22-30 Freescale Semiconductor Preliminary Appendix A 56F8323EVM Schematics 56F8323EVM Schematics, Rev. 2Freescale Semiconductor Appendix A-1 Preliminary A p p e n d i A B C D E x A U1 - 2 22 3 MISO0 24 MISO0/RXD1/PB1 PWMA0/PA0 4 PWMA0 +3.3V VDDcore MOSI0 MOSI0/PB2 PWMA1/PA1 PWMA1 25 7 SCLK0 SCLK0/PB3 PWMA2/SS1/PA2 PWMA2 /SS0 21 SS0/TXD1/PB0 PWMA3/MISO1/PA3 8 PWMA3 R76 R70 9 VDD_IO1 VCAP1 DNP PWMA4/MOSI1/PA4 PWMA4 1 10 4 TC0 TC0/TXD0/PC6 PWMA5/SCLK1/PA5 PWMA5 0 Ohm 0 Ohm 4 64 16 TC1 TC1/RXD0/PC5 ISA0/PA9 ISA0 63 18 TC3 TC3/P ISA1/PA10 ISA1 ISA2/PA11 19 ISA2 R77 R71 62 13 VDD_IO2 VCAP2 DNP CAN_TX CAN_TX/PC3 FAULTA0/PA6 FAULTA0 61 14 CAN_RX CAN_RX/PC2 FAULTA1/PA7 FAULTA1 0 Ohm 0 Ohm 15 FAULTA2/PA8 FAULTA2 12 /IRQA IRQA /RESET 2 RESET PHA0/TA0/PB7 52 PHASEA0 R78 R72 51 VDD_IO3 VCAP3 DNP PHB0/TA1/PB6 PHASEB0 47 50 XTAL XTAL/PC1 INDEX0/TA2/PB5 INDEX0 0 Ohm 0 Ohm 46 49 EXTAL EXTAL/PC0 HOME0/TA3/PB4 HOME0 TDI 55 TDI ANA0 26 ANA0 R79 R73 56 27 VDD_IO4 VCAP4 DNP TDO TDO ANA1 ANA1 53 28 M TCK TCK ANA2 ANA2 0 Ohm 0 Ohm 58 29 /TRST TRST ANA3 ANA3 C TMS 54 TMS ANA4 30 ANA4 5 3 31 3 ANA5 ANA5 6 +3.3V_PLL 42 32 ANA6 F VDAA_OSC_PLL ANA6 33 JG6 8 ANA7 ANA7 40 ANA7 3 +VREFH VREFH 2 34 TEMP_SENSE 2 VDD_IO1 TEMP_SENSE 1 3 6 VDD_IO1 R80 E VDD_IO2 20 41 VA VDD_IO2 VDDA_ADC +3.3VA V VDD_IO3 48 VDD_IO3 0 Ohm VDD_IO4 M 59 C5 1 2 R15 VDD_IO4 FAULTA0 0.1uF 0.001uF 100pF U OCR_DIS 45 OCR_DIS 47K s 39 VSSA_ADC e VCAP1 57 VCAP1 Single trace r VCAP2 23 37 VREFP VCAP2 VREFP to GNDA R16 M VCAP3 5 VCAP3 VREFMID 36 VREFM FAULTA1 a C1 VCAP4 43 35 VREFN VCAP4 VREFN 47K n 2.2uF C2 u 2 2.2uF C3 11 VSS_IO1 C6 C7 C8 2 a 2.2uF 17 0.1uF 0.1uF 0.1uF R17 l VSS_IO2 , 2.2uF 44 FAULTA2 VSS_IO3 R 60 38 VSS_IO4 VREFLO 47K e Single trace v to GNDA . MC56F8323FG60 2 DSP Standard Products Division +3.3V 2100 East Elliot Road Tempe, Arizona 85284 R74 480 413-5090 FAX: 480 413-2510 1K 1 ON-CHIP CORE REGULATOR 1 JG12 Title ENABLE REGULATOR 1-2 MC56F8323 Processor F 1 OCR_DIS r e 2 DISABLE REGULATOR N/C Document Rev. e Size Number MC56F8323EVM.DSN s c 1.1 a A l Date: Monday, May 12, 2003 Designer: DSPO Design Sheet 1 of 13 e A B C D E S e P m i r c e o l Figure A-1. 56F8323 Processor i n m d i u n c a t r oy r P F r r e e l e i m s i c n a A B C D E a l r ey S e m JG1 +3.3V i c 1 GPIOC0 R25 o 2 EXTAL n JG7 3 10K d User u 1 OSC BYPASS GPIOB3 Jumper c 4 SCLK0 2 4 Y1 1M t 3 #0 o 8.00MHz R14 r R26 1K JG2 1 GPIOC1 2 XTAL SOFTWARE FEATURE JUMPERS +3.3V +3.3V R27 JG8 R23 10K User 1 GPIOB0 5 10K /SS0 2 Jumper 6 3 3 #1 3 F S1 R28 8 3 /POR 2 1K RESET PUSHBUTTON 3 E V M S +3.3V c h e OPTIONAL m R24 a IRQA PUSHBUTTON 10K t +3.3V i c S2 s U2 , 2 /IRQA 2 2 R Vcc 1 /POR e RST 3 C9 v GND 0.1uF . 2 DS1818 DNP DSP Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 3 480 413-5090 FAX: 480 413-2510 DS1818 1 1 1 2 Title RESET, CLOCK & IRQ Document Rev. Size Number MC56F8323EVM.DSN A 1.1 Date: Monday, May 12, 2003 Designer: DSPO Design Sheet 2 of 13 A B C D E A p p e n Figure A-2. Reset, Clock & IRQ d i x A - 3 A p p e n d i A B C D E x A - 4 +3.3V U3 28 26 C1+ VCC C32 1.0uF 3 C34 4 V- 4 24 1.0uF C1- 1 C2+ C33 27 C35 V+ 1.0uF 1.0uF 2 25 C2- GND P2 1 DCD JG5 6 DSR TXD1 14 9 TXD 2 /SS0 1 2 T1IN T1OUT TXD RXD1 13 10 7 MISO0 3 4 T2IN T2OUT CTS T3IN 12 11 RXD 3 T3IN T3OUT 1 RXD RTS 8 RTS 20 4 1 R2OUTB DTR JG13 19 4 9 R1OUT R1IN RTS1 18 5 CTS 5 M 1 R2OUT R2IN CTS1 17 6 R3IN 2 1 R3OUT R3IN C 16 7 R4IN 1 R4OUT R4IN 5 3 RTS/CTS +3.3V 1 15 R5OUT R5IN 8 R5IN SCI #1 3 6 F /EN 23 RS-232 8 FORCEON 21 3 INVALID 1 R29 22 2 RS-232 SHUTDOWN JUMPER FORCEOFF CONNECTOR 1K 3 E MAX3245EEAI V RS-232 ENABLE N/C JG4 M 1 2 U RS-232 DISABLE 1 - 2 s e r M a n u 2 2 a l , +3.3V R R30 e /EN v 1K . 2 R32 T3IN 1K DSP Standard Products Division R34 2100 East Elliot Road R3IN 1K Tempe, Arizona 85284 R35 480 413-5090 FAX: 480 413-2510 R4IN 1 1 1K Title RS-232 AND SCI CONNECTORS F R36 r R5IN e Document Rev. e 1K Size Number MC56F8323EVM.DSN s c 1.1 a A l Date: Monday, May 12, 2003 Designer: DSPO Design Sheet 3 of 13 e A B C D E S e P m i r c e o l Figure A-3. RS-232 and SCI Connectors i n m d i u n c a t r oy r P F r r e e l e i m s i c n a A B C D E a l r ey S e m i c o n OPTIONAL d u c 4 4 t o r U5 20 2 SERIAL D/A CONNECTOR +3.3V VDD FBA J4 9 3 D/A0 MOSI0 DIN OUTA 1 2 JG9 D/A1 3 4 12 4 D/A2 1 DOUT OUTB 5 6 D/A3 MISO0 2 7 8 10 5 SCLK0 SCLK FBB SPI0 DNP DAISYCHAIN 6 REFAB +Vref DNP 15 +3.3VA REFCD 5 8 /SS0 CS 6 3 16 3 FBC F /RESET 7 CL 8 17 3 OUTC +Vref R48 2 18 1K POT 3 R58 OUTD DNP E 14 +3.3V PDL 19 V Set to 2.7V 5.1K FBD M DNP 13 UP0 1 S c 11 1 DGND AGND h e MAX5251BEAP m DNP a t i c s , 2 2 R e v . 2 DSP Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 480 413-5090 FAX: 480 413-2510 1 1 Title DEBUG SERIAL 4-CHANNEL D/A CONVERTER Document Rev. Size Number MC56F8323EVM.DSN A 1.1 Date: Monday, May 12, 2003 Designer: DSPO Design Sheet 4 of 13 A B C D E A p p e n Figure A-4. Debug Serial 4-Channel D/A Converter d i x A - 5 A p p e n d i A B C D E x A - 6 +3.3V U6A LED7 R7 YELLOW LED PA0 1 2 4 PWMA0 4 270 74AC04 U6B LED8 R8 GREEN LED PA1 3 4 PWMA1 270 74AC04 U6C LED9 R9 YELLOW LED PA2 5 6 PWM STATE PWMA2 M 270 C 74AC04 5 3 3 6 U6D LEDS F LED10 GREEN LED 8 R10 PA3 9 8 3 PWMA3 2 270 3 E 74AC04 V M U6E LED11 R11 YELLOW LED U PWMA4 PA4 11 10 s 270 e r 74AC04 M a U6F LED12 n R12 GREEN LED u PA5 13 12 2 PWMA5 2 a l 270 , R 74AC04 e v . 2 DSP Standard Products Division 2100 East Elliot Road Tempe, Arizona 85284 480 413-5090 FAX: 480 413-2510 1 1 Title PWM PORT A STATE LEDS F r e Document Rev. e Size Number MC56F8323EVM.DSN s c 1.1 a A Date: Monday, May 12, 2003 Designer: DSPO Design Sheet 5 of 13 l e A B C D E S e P m i r c e o l Figure A-5. PWM Port A State LEDs i n m d i u n c a t r oy r P F r r e e l e i m s i c n a A B C D E a l r ey S +3.3V e U7A m LED1 R1 RED LED PC0 i 1 2 c EXTAL o 270 n d

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