tms320vc5509_tms320vc5416_tms320vc5416中文资料(2)

014000h ? 015FFFh SARAM 2 02C000h ? 02DFFFh SARAM 14

016000h ? 017FFFh SARAM 3 02E000h ? 02FFFFh SARAM 15

018000h ? 019FFFh SARAM 4 030000h ? 031FFFh SARAM 16

01A000h ? 01BFFFh SARAM 5 032000h ? 033FFFh SARAM 17

01C000h ? 01DFFFh SARAM 6 034000h ? 035FFFh SARAM 18

01E000h ? 01FFFFh SARAM 7 036000h ? 037FFFh SARAM 19

020000h ? 021FFFh SARAM 8 038000h ? 039FFFh SARAM 20

022000h ? 023FFFh SARAM 9 03A000h ? 03BFFFh SARAM 21

024000h ? 025FFFh SARAM 10 03C000h ? 03DFFFh SARAM 22

026000h ? 027FFFh SARAM 11 03E000h ? 03FFFFh SARAM 23

3.1.3 On-Chip Read-Only Memory (ROM)

The one-wait-state ROM is located at the byte address range FF0000h?FFFFFFh. The ROM is composed of one block of 32K bytes and two 16K-byte blocks, for a total of 64K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the

internal ROM.

NOTE: Customers can arrange to have the 5509A ROM programmed with contents unique to any particular application. Contact your local Texas Instruments representative for more information on custom ROM programming.

The standard 5509A device includes a bootloader program resident in the ROM. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is

disabled and not present in the memory map, and byte address range FF0000h?FFFFFFh is directed to external memory space. A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect the MPNMC bit. All three ROM blocks can be accessed by the program, data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two cycles per 16-bit word.

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