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ModelSim eases the process of finding design defects with an intelligently engineered debug environment.

The ModelSim debug environment efficiently displays design data for ysis and debug of all languages. ModelSim allows many debug and ysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.

Unified mixed language simulation engine for ease of use and performance

Native support of Verilog, SystemVerilog for design, and VHDL, for effective verification of sophisticated design environments

Fast time-to-debug, easy to use, multi-language debug environment

Advanced code coverage and ysis tools for fast time to coverage closure

Interactive and Post-Sim Debug available so same debug environment used for both

Powerful Waveform Compare for easy ysis of differences and bugs

Advanced code coverage and ysis tools for fast time to coverage closure

Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project

Assertions

Gain insight and visibility into your design by letting assertions notify you of an error so it can be fixed

ModelSim provides a powerful library of checkers (OVL) letting you debug with assertions right away, without writing your own

Assertions can also serve as documentation for your design, as comments are embedded into the code as you go

Download ModelSim PE for a risk-free, 21-day trial of the industrys leading simulator with full mixed-language support for VHDL, Verilog, SystemVerilog, and a comprehensive debug environment including code coverage.

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