基 于 VHDL 的 万 年 历 设 计（ＥＤＡ实验报告）.doc(3)

输入的上层原理图如图4所示。目标芯片选择EP1K30TC144-3，实验箱中的电容结构选择模式NO.3，如图21所示，其自身附带了表明译码的系统，无需在流程、原理图中设计七段显示译码的系统就可以在数码管中进行显示，同时配置有8个按键输入端。图21 实验电源No.34.3.2端口配置 将上层原理图中输入输出端引脚与试验箱中的输入输出引脚进行匹配，才可以进行下载验证。表1 GW48CK/GK/EK/PK2 系统万能接接口与信号/与芯片电阻对照表上的讯号名GW48-CCP，GWAK100AEP1K100QC208GW48-SOC+/ GW48-DSPEP20K200/300EQC240GWAK30/50EP1K30/50TQC144GWAC3EP1C3TC144引脚号引脚名称引脚号跳线名称引脚号跳线名称引脚号跳线名称PIO07I/O224I/O08I/O01I/O0PIO18I/O225I/O19I/O12I/O1PIO29I/O226I/O210I/O23I/O2PIO311I/O231I/O312I/O34I/O3PIO412I/O230I/O413I/O45I/O4PIO513I/O232I/O517I/O56I/O5PIO614I/O233I/O618I/O67I/O6PIO715I/O234I/O719I/O710I/O7PIO817I/O235I/O820I/O811DPCLK1PIO918I/O236I/O921I/O932VREF2B1PIO1024I/O237I/O1022I/O1033I/O10PIO1125I/O238I/O1123I/O1134I/O11PIO1226I/O239I/O1226I/O1235I/O12PIO1327I/O2I/O1327I/O1336I/O13PIO1428I/O3I/O1428I/O1437I/O14PIO1529I/O4I/O1529I/O1538I/O15PIO1630I/O7I/O1630I/O1639I/O16PIO1731I/O8I/O1731I/O1740I/O17PIO1836I/O9I/O1832I/O1841I/O18PIO1937I/O10I/O1933I/O1942I/O19PIO2038I/O11I/O2036I/O2047I/O20PIO2139I/O13I/O2137I/O2148I/O21PIO2240I/O16I/O2238I/O2249I/O22PIO2341I/O17I/O2339I/O2350I/O23PIO2444I/O18I/O2441I/O2451I/O24PIO2545I/O20I/O2542I/O2552I/O25PIO26113I/O131I/O2665I/O2667I/O26PIO27114I/O133I/O2767I/O2768I/O27PIO28115I/O134I/O2868I/O2869I/O28PIO29116I/O135I/O2969I/O2970I/O29PIO30119I/O136I/O3070I/O3071I/O30PIO31120I/O138I/O3172I/O3172I/O31PIO32121I/O143I/O3273I/O3273I/O32PIO33122I/O156I/O3378I/O3374I/O33PIO34125I/O157I/O3479I/O3475I/O34PIO35126I/O160I/O3580I/O3576I/O35PIO36127I/O161I/O3681I/O3677I/O36PIO37128I/O163I/O3782I/O3778I/O37PIO38131I/O164I/O3883I/O3883I/O38PIO39132I/O166I/O3986I/O3984I/O39PIO40133I/O169I/O4087I/O4085I/O40PIO41134I/O170I/O4188I/O4196I/O41PIO42135I/O171I/O4289I/O4297I/O42PIO43136I/O172I/O4390I/O4398I/O43PIO44139I/O173I/O4491I/O4499I/O44PIO45140I/O174I/O4592I/O45103I/O45PIO46141I/O178I/O4695I/O46105I/O46PIO47142I/O180I/O4796I/O47106I/O47PIO48143I/O182I/O4897I/O48107I/O48PIO49144I/O183I/O4998I/O49108I/O49PIO60202PIO60223PIO60137PIO60131PIO60PIO61203PIO61222PIO61138PIO61132PIO61PIO62204PIO62221PIO62140PIO62133PIO62PIO63205PIO63220PIO63141PIO63134PIO63PIO64206PIO64219PIO64142PIO64139PIO64PIO65207PIO65217PIO65143PIO65140PIO65PIO66208PIO66216PIO66144PIO66141PIO66PIO6710PIO67215PIO677PIO67142PIO67PIO6899PIO68197PIO68119PIO68122PIO68PIO69100PIO69198PIO69118PIO69121PIO69PIO70101PIO70200PIO70117PIO70120PIO70PIO71102PIO71201PIO71116PIO71119PIO71PIO72103PIO72202PIO72114PIO72114PIO72PIO73104PIO73203PIO73113PIO73113PIO73PIO74111PIO74204PIO74112PIO74112PIO74PIO75112PIO75205PIO75111PIO75111PIO75PIO7616PIO76212PIO7611PIO76143PIO76PIO7719PIO77209PIO7714PIO77144PIO77PIO78147PIO78206PIO78110PIO78110PIO78PIO79149PIO79207PIO79109PIO79109PIO79SPEAKER148I/O184I/O99I/O50129I/OCLOCK0182I/O185I/O126INPUT1123I/OCLOCK2184I/O181I/O54INPUT3124I/OCLOCK578I/O151CLKIN56I/O53125I/OCLOCK980I/O154CLKIN124GCLOK2128I/O目标芯片选择的是EP1K30TC144-3，根据图21和表1中诱发的部份引脚对照表，顶层原理图的输入输出端口配置如图22所示。

例如CLK时钟输入配置为54引脚，根据表1所示，实验箱上实际电容所用的输入时钟信号选用CLK2。按键K1、K2、K3分别配置8、9、10引脚，由表1知，在试验上对应的是PIO、PIO1、PIO3，再由图21知对应的中控分别是中控1、按键2、按键3，验证时，通过按这三个键来对万年历功能进行控制。图22 端口配置图4.3.3实际电容验证图23实际电容验证 实际验证电路和验证结果如上图23所示。验证结果与预期的试验结果相近，当K1键没有按下时，万年历正常计时，计满向低位进位，可以通过K3键选择显示模式，显示时分秒时指示灯亮。通过按下K1键的次数来选择校对那一部分，对应的指示灯亮，再借助按下K2键的次数来进行差值选择，进行校对时短期不会向低位进位。当把年增设为闰月，月系统设置为2月，天系统设置为29，时系统设置为23，分系统设置为59，通过中控K1选择正常计时模式，计满60s时，不断往上进位，月份变为3月，证明此时二月为二十九进制计数器。4.4实验小结通过上次基于VHDL万年历设计311HZ晶体振荡器电路分频器电路分频器电路校分控制电路校时控制电阻秒个位计数秒十位计数分个位计数分十位计数时个位计数时十位计数译码驱动译码驱动译码驱动译码驱动译码驱动译码驱动

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