十六进制计算器_设计60进制的计数器_60进制计算器

《60进制计加法数器的设计》 设计报告 姓 名： 赵思磊学 号： 0503100119班 级： 应用电子1001系 别： 电子工程系指导教师： 杨旭 、张楠时 间： 2012-5-28—2012-6-1 目 录 1.概述······································································21.1计数器设计目的················································31.2计数器设计组成················································32.六十进制计数器设计描述···········································42.1设计的思路·······················································62.2设计的实现·······················································63. 六十进制计数器的设计与仿真····································73.1基本电路分析设计··············································73.2 计数器电路的仿真·············································104.总结········································································134.1遇到的问题及解决方法········································134.2实验的体会与收获···············································14 1概述计数器是一个用以实现计数功能的时序部件，它不仅可用来及脉冲数，还常用作数子系统的定时、分频和执行数字运算以及其它特定的逻辑功能。设计60进制的计数器

??? 计数器种类很多。按构成计数器中的各触发器是否使用一个时钟脉冲源来分，有同步计数器和异步计数器。根据计数制的不同，分为二进制计数器、十进制计数器和任意进制计数器。根据计数器的增减趋势，又分为加法、减法和可逆计数器。设计60进制的计数器还有可预制数和可变程序功能计数器等等。目前，无论是TTL还是CMOS集成电路，都有品种较齐全的中规模集成计数器。使用者只要借助于器件手册提供的功能和工作波形图以及引出端的排列，就能正确运用这些器件。计数器在现代社会中用途中十分广泛，在工业生产、各种和记数有关电子产品。如定时器，、时钟电路中都有广泛用途。在配合各种显示器件的情况下实现实时监控，扩展更。1.1计数器设计目的每隔1s，计数器增1；能以数字形式显示时间。熟练掌握计数器的各个部分的结构。计数器间的级联。不同芯片也可实现六十进制。1.2计数器设计组成用两个74ls192芯片和一个与非门实现。当定时器递增到59时，定时器会自动返回到00显示，然后继续计时。本设计主要设备是两个74LS160同步十进制计数器，并且由200HZ，5V电源供给。作高位芯片与作低芯片位之间级联。两个芯片间的级联。2.六十进制计数器设计描述2.1设计的思路芯片介绍：74LS192 为加减可逆十进制计数器，CPU端是加计数器时钟信号，CPD是减计数时钟信号RD 1 时无论时钟脉冲状态如何，直接完成清零功能。

本文来自电脑杂谈，转载请注明本文网址：
http://www.pc-fly.com/a/jisuanjixue/article-31840-1.html