4 * 4矩阵键盘原理分析和代码显示

矩阵键盘的原理简介:

矩阵键盘的4个输入端口ROW [3: 0]接收FPGA产生的键盘扫描输入信号，而4个输出COL [3: 0]输入键盘操作的信息变化到FPGA扫描分析电路，然后获取按钮的操作代码.

输入端口分别连接到4个上拉电阻. 当4个输入端口的输入均为1时，无论按下哪个按钮，输出均为1，因此，如果将4个输入端口分配在开头0，则只要按任意键，键盘上的4个输出绝对会从1变为0，您可以确定它是哪一列，但是您不知道它是哪一行，因此此时使用键盘扫描. 键盘扫描是指只要输入端口的一行为0，其余三行均为1，则依次扫描即可轻松确定按键的准确值.

由于在实际使用中按下按钮时会出现抖动，因此需要消除抖动. 去抖动模块可以具有许多方法，例如状态机的去抖动方法和抽头延迟. 或者，因为这是一个键值输入，所以如果您想使用拍子延迟方法进行去抖动处理，则需要对其进行一些更改，并将相位更改为等于和更改相位以增加时钟时间.

下面给出了两种用于矩阵键盘实现的代码，其中之一是指赵然书中提到的夏玉文老师提供的代码. 这里使用状态机模块来消除抖动.

`define OK 1'b1    
`define NO 1'b0    
`define NoKeyIsPressed 17    
 
module keyscan0(clk,rst_n,keyscan,keyin,real_number);
 input clk,rst_n;
 input [3:0]keyin;
 output [3:0] keyscan;
 output [4:0] real_number;
 reg [3:0] state;
 reg [3:0] four_state; 
 reg [3:0] scancode,scan_state;
 reg [4:0] numberout,number_reg,number_reg1,number_reg2, real_number;   
 reg AnyKeyPressed;
 
 assign keyscan = scancode;
 
 always @(posedge clk or negedge rst_n)  
 if (!rst_n)
      begin
        scancode <=4'b0000;
        scan_state<= 4'b0000;
      end
 else
     if(AnyKeyPressed)
        case (scan_state)
            4'b0000: begin scancode<=4'b1110; scan_state<= 4'b0001; end
            4'b0001: begin  scancode <= {scancode[0],scancode[3:1]}; end      
        endcase 
     else  
        begin
            scancode <=4'b0000;
            scan_state<= 4'b0000;
        end  
 always @(posedge clk )   
 if( !(&keyin))
    begin
     AnyKeyPressed <= `OK ;  
     four_state <= 4'b0000;
    end
 else 
    if(AnyKeyPressed)
       case(four_state)
         4'b0000: begin  AnyKeyPressed <= `OK ;  four_state<=4'b0001; end
         4'b0001: begin  AnyKeyPressed <= `OK ;  four_state<=4'b0010; end
         4'b0010: begin  AnyKeyPressed <= `OK ;  four_state<=4'b0100; end
         4'b0100: begin  AnyKeyPressed <= `OK ;  four_state<=4'b1000; end
         4'b1000: begin  AnyKeyPressed <= `NO ;   end
         default: AnyKeyPressed <= `NO ;
       endcase
    else 
         four_state <= 4'b0000;
         
always @(posedge clk or negedge rst_n)
   if(!rst_n) 
        numberout<=`NoKeyIsPressed;
    else
  casex({scancode,keyin})
    8'b0111_1110: numberout <= 5'd10;
    8'b1011_1110: numberout <= 5'd3;  
    8'b1101_1110: numberout <= 5'd2;
    8'b1110_1110: numberout <= 5'd1; 
    
    8'b0111_1101: numberout <= 5'd11;
    8'b1011_1101: numberout <= 5'd6;  
    8'b1101_1101: numberout <= 5'd5;
    8'b1110_1101: numberout <= 5'd4; 
        
    8'b0111_1011: numberout <= 5'd12;
    8'b1011_1011: numberout <= 5'd9; 
    8'b1101_1011: numberout <= 5'd8;
    8'b1110_1011: numberout <= 5'd7; 
    
    8'b0111_0111: numberout <= 5'd13;
    8'b1011_0111: numberout <= 5'd15;  
    8'b1101_0111: numberout <= 5'd14;
    8'b1110_0111: numberout <= 5'd0; 
    default: numberout <=`NoKeyIsPressed;
   endcase
   
always @(posedge clk or negedge rst_n)     
begin
    if (!rst_n)
    begin
      number_reg <= 0;
    end
    else
        if( numberout<=5'd15 && numberout>=5'd0)
            begin
                 number_reg <= numberout;  
            end
        else
            begin
                if(AnyKeyPressed == `NO)
                    number_reg <= `NoKeyIsPressed;  
            end
           
 end
         
always @(posedge clk or negedge rst_n) 
 if (!rst_n)
    state <= 4'b0000;
 else 
    case (state)
4'd0: begin   
            number_reg1 <= number_reg;
            state <=4'd1;
        end
4'd1: begin 
            if(number_reg == number_reg1)
                state <= 4'd2;
            else
                state <= 4'd0;
        end
4'd2: begin
            if (number_reg == number_reg1)                  
                state <= 4'd3;
            else
                state <= 4'd0;
        end                     
4'd3: begin
            if (number_reg == number_reg1)                
                state <= 4'd4;
            else
                state <= 4'd0;   
        end          
4'd4: begin   
             if(number_reg == number_reg1)
                state <=4'd5;
             else
                state <= 4'd0; 
        end
4'd5: begin 
            if(number_reg == number_reg1)
                state <= 4'd6;
            else
                state <= 4'd0;
        end
4'd6: begin
            if (number_reg == number_reg1)                  
                state <= 4'd7;
            else
                state <= 4'd0;
        end                     
4'd7: begin
            if (number_reg == number_reg1)                
                  state <= 4'd8;
            else
                  state <= 4'd0;   
        end          
4'd8: begin 
            if (number_reg == number_reg1)    
                  state <=4'd9;
            else
                  state <= 4'd0;  
        end
4'd9: begin 
            if(number_reg == number_reg1)
                  state <= 4'd10;
            else
                  state <= 4'd0;
        end
4'd10: begin
            if (number_reg == number_reg1)                  
                  state <= 4'd11;
            else
                 state <= 4'd0;
        end                     
4'd11: begin
            if (number_reg == number_reg1)                
                 state <= 4'd12;
            else
                 state <= 4'd0;   
        end          
4'd12: begin 
            if(number_reg == number_reg1)
              state <= 4'd13;
            else
              state <= 4'd0;
        end
4'd13: begin
            if (number_reg == number_reg1)                  
                  state <= 4'd14;
            else
                 state <= 4'd0;
        end                     
4'd14: begin
            if (number_reg == number_reg1)                
             state <= 4'd15;
            else
             state <= 4'd0;   
        end                 
4'd15: begin
            if (number_reg == number_reg1 ) 
                begin                 
                    state <= 4'd0;
                    real_number <=number_reg; 
                end
            else
                         state <= 4'b0000;   
        end                        
  default:   state <= 4'b0000;   
  endcase   
endmodule

另一个:

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